CD4027 IC – Dual J-K Master-Slave Flip-Flop CD4027BE

Set-Reset capability
Static flip-flop operation — retains state indefinitely with clock level either "high" or "low"
Medium speed operation — 16 MHz (typ.) clock toggle rate at 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
5-V, 10-V, and 15-V parametric ratings