74LS73 IC Dual J-K Flip-Flop with Clear

Product Overview: A dual negative-edge-triggered master-slave J-K flip-flop integrated circuit containing two independent flip-flops with complementary outputs, designed for digital logic, state storage, and sequential circuit applications.

Core Specifications:

Manufacturer: Fairchild Semiconductor

Package Type: 14-lead PDIP, 14-lead SOIC

Function: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

Input Channels: J, K, Clock, and Clear (per flip-flop)

Control Interface: Logic-level signal triggering (Negative-edge-triggered)