74LS112 IC Dual JK Flip-Flop with Preset and Clear DIP-14 74LS112

Product Overview

The 74LS112A is a dual J-K flip-flop device containing two independent flip-flops, each featuring individual J, K, clock, preset, and clear inputs. This device operates using negative-edge triggering, where state changes occur on the high-to-low transition of the clock signal. It includes asynchronous PRESET and CLEAR inputs that, when pulled LOW, override all other signals to set or reset the outputs, respectively.

Core Specifications

• Manufacturer: Texas Instruments

• Package Type: Available in various packages, including Plastic Small-Outline (SOIC), Ceramic Chip Carriers, Flat Packages, and standard Plastic/Ceramic DIPs.

• Function: Dual (2-bit) negative-edge-triggered J-K flip-flops with asynchronous PRESET and CLEAR.